1. Field of the Invention
The present invention relates to a semiconductor device and a process for manufacturing the same and in particular to a semiconductor device having a polycrystalline silicon (or polysilicon) resistor layer and bipolar transistors and a process for manufacturing the same.
2. Description of the Prior Art
The emitter coupled logic (ECL) circuit comprises NPN type bipolar transistor elements and resistor elements as basic structural elements. A circuit diagram of the simplest invertor circuit is exemplarily shown in FIG. 1. The invertor circuit comprises a total of four transistor elements, Q.sub.1, Q.sub.2, Q.sub.3 and Q.sub.4 and a total of four resistor elements, R.sub.1, S.sub.2, R.sub.3 and R.sub.4.
FIGS. 2 through 5 are sectional views of a semiconductor chip sequentially showing a process for manufacturing a prior art semiconductor device in the order of steps.
As shown in FIG. 2, an N.sup.+ type buried layer 2 and an N.sup.- type epitaxial layer 3 are formed on a P type silicon substrate 1 and element isolating grooves are provided and element isolating layers 31 are buried in the groove to divide element forming regions and a silicon oxide film 6 is formed over the entire surface of the device. The element isolating layers 31 are formed as follows: A silica film (hereinafter referred to as a BPSG film) containing boron and phosphorus (Boro-Phospho-Silicate Glass) is deposited on the surface of the device including the grooves by the low-pressure or evacuated CVD method or the like. Thereafter, the BPSG film is buried in only the grooves by etching back the BPSG film. Accordingly, a more or less depression may be formed in each of the grooves due to variation in the etch back.
Then, as shown in FIG. 3, a polycrystalline silicon layer is deposited over an entire surface of the device and boron is ion implanted into the polycrystalline silicon layer. The polycrystalline silicon layer is patterned to form a base leading electrode 9a and a resistor layer 9b.
Then, as shown in FIG. 4, a silicon nitride film 10 is deposited over the entire surface of the device. The silicon nitride film 10 and the base leading electrodes 9a are selectively and sequentially removed by etching to form openings. Undercut portions 15 are formed under the base leading electrode 9a by etching the silicon oxide film 6 using the silicon nitride film 10 as a mask.
A thin polycrystalline silicon layer 16 (FIG. 5) is deposited over the entire surface of the device to fill the undercut portions 15 (FIG. 4) as shown in. The deposited thin polycrystalline silicon layer 16 is converted into a silicon oxide film by the thermal oxidation except for the layer filling the undercut portions 15. The polycrystalline silicon layer 16 is buried in only the undercut portions 15 by etching the silicon oxide film. The impurity contained in the base leading electrode 9a is introduced into the silicon substrate 1 via the polycrystalline silicon layer 16 to form a graft base region 17. Subsequently, a base region 18 is formed by ion implanting boron into the silicon substrate 1 in the opening. A silicon nitride film 19 is formed over the entire surface of the device and is etched back to leave the silicon nitride film 19 only on the side of the opening so that a side wall is formed. A polycrystalline silicon layer 20 containing an N type impurity or dopant is deposited on the surface of the device including the opening. An impurity is introduced on the surface of the base region 18 from the polycrystalline silicon layer 20 to form an emitter region 21. The semiconductor device is thus completed by providing the silicon nitride film 10 on the resistor layer 9b with contact holes.
Since, in the prior semiconductor device as mentioned above, the base leading electrodes and the resistor layers are provided in the same layer by patterning the same polycrystalline silicon layer, they cannot be provided in the vicinity of transistors and are disposed in positions remote from the transistor region. Accordingly, such prior semiconductor device has a problem that wirings become long to prevent the circuits from being integrated, resulting in that an improvement in circuit characteristics is difficult.
If base leading electrodes and resistor layers are tried to be formed of the same layer between transistors which are disposed at the minimum occupation area in each of element forming regions which are isolated by element isolating layers, the spacing between the adjacent transistors is about double as wide as the minimum line width in consideration of the margin for an emitter contact and a base leading electrode even when the emitter size is reduced to about the minimum line width. Therefore, the base leading electrodes and the resistor layers cannot be disposed in the same layer between the transistors.
Even if the resistor layers can be disposed between the transistors by increasing the spacing between the transistors, the resistor layers would traverse across the element isolating layers thereabove. The resistor layers would be influenced by steps of the element isolating layer which are caused by etch back or the like. The variations in the value of resistance would become larger. The variations in resistance value in usual ECL circuit is undesirable since it should be suppressed within several % in terms of relative value.